The present disclosure relates to a solid-state imaging device and electronic equipment such as a camera provided with the solid-state imaging device.
As a solid-state imaging device, there is an amplification type solid-state imaging device represented by an MOS-type image sensor such as a CMOS (Complementary Metal Oxide Semiconductor). In addition, there is a charge-transfer type solid-state imaging device represented by a CCD (Charge Coupled Device) image sensor. The solid-state imaging devices are widely used in digital still cameras, digital video cameras, and the like. In recent years, as a solid-state imaging device mounted on mobile equipment including mobile telephones with camera, PDAs (Personal Digital Assistants), and the like, the MOS-type image sensor is widely used in the light of power consumption as the voltage of the power supply is low.
Such an MOS-type solid-state imaging device is formed of a photodiode of which a unit pixel serves as a photoelectric conversion unit and a plurality of pixel transistors, and is configured to have a pixel array in which a plurality of unit pixels is arrayed in a two-dimensional array shape (pixel area) and the peripheral circuit area. The plurality of pixel transistors is formed with MOS transistors, and configured to include three transistors of a transfer transistor, a reset transistor, an amplification transistor, or four transistors by adding a selection transistor thereto.
In such MOS-type solid-state imaging devices of the related art, solid-state imaging devices have been variously proposed, which is configured to be one device by electrically connecting a semiconductor chip, in which a pixel array arranged with a plurality of pixels is formed, and a semiconductor chip, in which a logic circuit performing signal processing is formed. For example, in Japanese Unexamined Patent Application Publication No. 2006-49361, a semiconductor module is disclosed, in which a backside illumination type image sensor chip having micro-pads for each pixel cell and a signal processing chip having micro-pads formed with a signal processing circuit are connected to each other by micro-bumps.
In International Publication No. WO 2006/129762, a semiconductor image sensor module is disclosed, in which a first semiconductor chip provided with an image sensor, a second semiconductor chip provided with an analog/digital converter array, and a third semiconductor chip provided with a memory element array are stacked. The first semiconductor chip and the second semiconductor chip are connected by a bump that is a conductive connection conductor. The second semiconductor chip and the third semiconductor chip are connected by a penetration contact which penetrates the second semiconductor chip.
As shown in Japanese Unexamined Patent Application Publication No. 2006-49361, and the like, a technique of mounting different kinds of circuit chips including an image sensor chip, a logic circuit performing signal processing, and the like by mixing has been variously proposed. In the related art, a through connection hole is formed in a state where functional chips are almost completed and connects the chips to each other, or the chips are connected to each other by a bump.